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HD74LV2GT123A
Retriggerable Monostable Multivibrator / CMOS Logic Level Shifter
REJ03D0004-0300Z Rev.3.00 Oct.22.2003
Description
The HD74LV2GT123A features output pulse duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The basic pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. Once triggered, the basic pulse duration can be extended by retriggering the gated low level active (A) or high level active (B) input. Pulse duration can be reduced by taking CLR low. The output pulse equation is simply : tWQ = Cext * Rext. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
* The basic gate function is lined up as Renesas uni logic series. * Supplied on emboss taping for high-speed automatic mounting. * Control input is TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : -40 to +85C * Logic-level translate function 3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V) * All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) * Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) * All the logical inputs have hysteresis voltage for the slow transition. * Ordering Information
Part Name HD74LV2GT123AUSE Package Type SSOP-8 pin Package Code TTP-8DBV Package Taping Abbreviation Abbreviation (Quantity) US E (3,000 pcs / Reel)
Rev.3.00, Oct.22.2003, page 1 of 1
HD74LV2GT123A
Outline and Article Indication
* HD74LV2GT123A
Index band Lot No.
YMW T23
SSOP-8 Marking
Y : Year code (the last digit of year) M : Month code W : Week code
Function Table
Inputs CLR L H H H H H : High level L : Low level X : Immaterial : Low to high transition : High to low transition : High level pulse A X H X L L B X X L H H Output Q L L L
Rev.3.00, Oct.22.2003, page 2 of 13
HD74LV2GT123A
Pin Arrangement
A
1
8
VCC
B
2
7
Rext / Cext
CLR
3
6
Cext
GND
4
5
Q
(Top view)
Absolute Maximum Ratings
Item Supply voltage range Input voltage range
*1
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 200 -65 to 150
Unit V V V mA mA mA mA mW C
Test Conditions
Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation *3 at Ta = 25C (in still air) Storage temperature Notes:
Output : H or L VCC : OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Rev.3.00, Oct.22.2003, page 3 of 13
HD74LV2GT123A
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH IOL Input transition rise or fall rate t / v External timing resistance External capacitance Supply transition rise rate Rext Cext t / VCC Min 3.0 0 0 -- -- -- -- 0 0 1 -- 1 -40 Typ -- -- -- -- -- -- -- -- -- -- Max 5.5 5.5 VCC -6 -12 6 12 100 20 -- k F ms / V C ns / V Unit V V V mA VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V Conditions
Unlimited --
-- --
-- 85
Operating free-air temperature Ta
Note: Unused or floating inputs must be held high or low.
Logic Diagram
Rext/ Cext
Cext
A
B Q Q
CLR CLR
Rev.3.00, Oct.22.2003, page 4 of 13
HD74LV2GT123A
Electrical Characteristic
* Ta = -40 to 85C
Item Input voltage Symbol VCC (V) * VIH VIL Hysteresis voltage VH VOH 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 3.3 5.0 Output voltage Min to Max 3.0 4.5 VOL Min to Max 3.0 4.5 Input current Input current Rext / Cext Quiescent supply current IIN IIN ICC ICC-T 0 to 5.5 5.5 5.5 5.5 Min 1.5 2.0 -- -- -- -- VCC-0.1 2.48 3.8 -- -- -- -- -- -- -- Typ -- -- -- -- 0.10 0.15 -- -- -- -- -- -- -- -- -- -- Max -- -- 0.6 0.8 -- -- -- -- -- 0.1 0.44 0.55 1 2.5 10 1.5 A A A mA V IOH = -50 A IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND VIN = VCC or GND, IO = 0 One input VIN = 3.4 V, other input VCC or GND VIN = VCC or GND Rext / Cext = 0.5VCC
VIN or VO = 0 to 5.5 V
Unit V
Test condition
V
VT+ - VT-
Active state supply current
ICC
4.5 5.5 0 5.0
-- -- -- --
-- -- -- 3.0
650 975 5 --
A A pF
Output leakage current IOFF Input capacitance CIN
VIN = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.3.00, Oct.22.2003, page 5 of 13
HD74LV2GT123A
Switching Characteristics
* VCC = 3.3 0.3 V
Ta = 25C Item Propagation delay time Symbol tPLH tPHL tPLH Output pulse width twQ Min -- -- -- -- -- -- -- 90 0.9 Pulse width tw 5.0 -- -- Typ 10.0 11.5 8.0 9.5 10.0 11.5 150 100 1.0 -- 30 1.2 Max 21.0 24.5 16.0 19.5 22.5 26.0 240 110 1.1 -- -- --
Ta = -40 to 85C
Test ns ns ns ns s ms ns ns s CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM A or B CLR
TO (Output) Q Q
Min 1.0 1.0 1.0 1.0 1.0 1.0 -- 90 0.9 5.0 -- --
Max 24.0 27.5 18.5 22.0 26.0 29.5 300 110 1.1 -- -- --
Unit Conditions (Input)
CLR Q (Trigger)
CL = 50 pF, Cext = 28 pF, Rext = 2 k CL = 50 pF, Cext = 0.01 F, Rext = 10 k CL = 50 pF, Cext = 0.1 F, Rext = 10 k A, B or CLR A or B (Rext = 1 k, Cext = 100 pF) A or B (Rext = 1 k, Cext = 0.01 F)
Retrigger time trr
* VCC = 5.0 0.5 V
Ta = 25C Item Propagation delay time Symbol tPLH tPHL tPLH Output pulse width twQ Min -- -- -- -- -- -- -- 90 0.9 Pulse width tw 5.0 -- -- Typ 7.3 8.5 5.9 7.5 7.3 8.7 140 100 1.0 -- 20 0.95 Max 12.0 14.0 9.4 11.4 12.9 14.9 200 110 1.1 -- -- --
Ta = -40 to 85C
Test
FROM A or B CLR
TO (Output) Q
Min 1.0 1.0 1.0 1.0 1.0 1.0 -- 90 0.9 5.0 -- --
Max 14.0 16.0 11.0 13.0 15.0 17.0 240 110 1.1 -- -- --
Unit Conditions (Input) ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns s ms ns ns s
Q
CLR Q (Trigger)
CL = 50 pF, Cext = 28 pF, Rext = 2 k CL = 50 pF, Cext = 0.01 F, Rext = 10 k CL = 50 pF, Cext = 0.1 F, Rext = 10 k A, B or CLR A or B (Rext = 1 k, Cext = 100 pF) A or B (Rext = 1 k, Cext = 0.01 F)
Retrigger time trr
Rev.3.00, Oct.22.2003, page 6 of 13
HD74LV2GT123A
Operating Characteristics
* CL = 50 pF
Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) Min 5.0 -- Typ 31.0 Max -- Unit pF Test Conditions f = 10 MHz
Test Circuit
VCC Cext
- +
Rext
Cext = 28 pF or 100 pF or 0.01 F or 0.1 F Rext = 1 k or 2 k or 5 k or 10 k
VCC
Input
See Function Table
Cext Rext/ Cext A B CLR GND
VCC
Q
Output C L = 15 pF or 50 pF
Note : C L includes the probe and jig capacitance.
Rev.3.00, Oct.22.2003, page 7 of 13
HD74LV2GT123A
Timing Diagram
t rr A
B CLR
Rext/ Cext Q tw tw t w +t rr
Caution in use In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible. Large values of Cext may cause problems when powering down the HD74LV2GT123A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from Vcc through the protection diodes at pin 7 pin. Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off time of the Vcc power supply must not be faster than t = Vcc * Cext/(20 mA). For example, if Vcc = 5 V and Cext = 22 F, the Vcc supply must turn off no faster than t = (5 V) * (22 F)/ 20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of Vcc to zero volts occurs, the HD74LV2GT123A may sustain damage. To avoid this possibility, use an external calmping diode. The input pins for unused circuit should be used under conditions to fix the outputs to avoid malfunction caused by noises. Also, it's recommended that Rext / Cext terminals are open and external parts are not connected to.
Rev.3.00, Oct.22.2003, page 8 of 13
HD74LV2GT123A
* Waveform - 1
90% Vref
tf VI 10% tr GND
Input A
Input B 10%
90% Vref tr tf 90% Vref 10% t w (L) t PLH (trigger) t PHL tr 90% Vref 10%
VI GND
Input CLR 10%
90% Vref
VI GND
VOH Output Q 50% 50% VOL
Rev.3.00, Oct.22.2003, page 9 of 13
HD74LV2GT123A
* Waveform - 2
tr 90% Vref 10% tf 90% Vref 10% 10% t w (L) 90% Vref 10%
tf
tr 90% Vref 10% t w (L) tf 90% Vref 90% Vref 10% t w (H) VI GND VI GND
Input A
t w (H) tr
Input B
VOH Output Q 50% t w (out) 50% VOL
* Waveform - 3
90% Vref
tf
tr 90% 10% tr 90% Vref 90% 10% 10% t rr tf 90% Vref
tf VI 10% tr 90% Vref 10% VI GND VOH GND
Input A
Input B
10%
Output Q
50% t w (out) + t rr
50% VOL
VCC (V) VI
INPUTS tr / tf
Vref 50% 1.5 V
3.30.3 2.5 V 3.0 ns 5.00.5 3V 3.0 ns
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 . 2. The output are measured one at a time with one transition per measurement.
Rev.3.00, Oct.22.2003, page 10 of 13
HD74LV2GT123A
Application Data
Vcc = 5.0 V 10000.0
tWQ (s) Output pulse width
1000.0
100.0
10.0 Rext 1.0 1 k 10 k 100 k 1 M
2 3 4 5 6 7
0.1 10
10
10
10
10
10
Timing capacitance
Cext (pF)
Vcc = 3.3 V 10000.0
tWQ (s) Output pulse width
1000.0
100.0
10.0 Rext 1.0 1 k 10 k 100 k 1 M
2 3 4 5 6 7
0.1 10
10
10
10
10
10
Timing capacitance
Cext (pF)
Rev.3.00, Oct.22.2003, page 11 of 13
HD74LV2GT123A
Rext = 2 k 1.4 Cext 1.3 1000 pF 10000 pF 100000 pF 1000000 pF
Coefficient of output pulse width
K
1.2
1.1
1.0
0.9
0.8 3.0 3.5 4.0 4.5 Supply voltage 5.0 VCC (V) 5.5 6.0
Rext = 10k
1.4
K
Cext
1.3
Coefficient of output pulse width
1000pF 10000pF 100000pF 1000000pF
1.2 1.1 1.0 0.9 0.8 3.0 3.5 4.0
Supply voltage
4.5
VCC (V)
5.0
5.5
6.0
Rev.3.00, Oct.22.2003, page 12 of 13
HD74LV2GT123A
Package Dimensions
2.0 0.2 1.5 0.2 (0.5) (0.5) (0.5)
(0.4)
Unit: mm
2.3 0.1
3.1 0.3
0 - 0.1
8 - 0.2 - 0.05
(0.17)
+ 0.1
0.7 0.1 (0.4)
Package Code JEDEC JEITA Mass (reference value)
TTP-8DBV 0.010 g
Rev.3.00, Oct.22.2003, page 13 of 13
0.13 - 0.05
+ 0.1
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